Automates metal and via stacking while checking design-rule compliance, reducing manual design effort and the likelihood of layout errors while supporting more efficient IC development.

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Manually arranging metal layers and vias in IC layouts can be time-consuming and may result in design-rule violations, unsuitable metal density or undesirable voltage-drop characteristics, increasing the complexity of physical chip design.

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Provides an automated IC-layout generation method that receives design parameters, selects relevant layers and automatically stacks metal layers and vias towards the topmost or bottommost layers at block and chip levels while checking design-rule compliance.

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Automates the stacking of metal layers and vias across IC blocks and chip levels while simultaneously checking design-rule compliance, reducing manual layout effort and potential design errors.

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