Inductance variation is inevitable after fabrication due to process variations and unpredicted parasitic.It is desired to have the flexibility for inductance fine tuning after fabrication. This is attractive as re-fabrication is costly.
1) Available fine tuning capability needs an additional structure which adds parasitic and degrades inductor performance
2) Available fine-tuning techniques are not feasible to integrate with monolithic inductors which their models are usually provided by the factory
3) In available fine-tuning techniques, the inductor physics need to be modified
The proposed inductor benefits from the idea of changing the magnetic field of monolithic planar inductor by shorting the metal shields to the ground. When all metal shields are shorted to the ground, the inductor shows its maximum inductance. The metal shields can be shorted one by one, which provides a fine tuning range.
1) No increase in the main cost of fabrication
2) No increase in design time
3) Easy to add the structure to the required planar inductor or component
4) No modification to the main inductor or component is required
5) It can be applied to GHz range and beyond
6) It compensates for the frequency drift due to the manufacturing variations with a fully-integrated solution
7) The requirement for off-chip frequency adjustment is eliminated
The technique uses the same IC fabrication process of the main design. It can be included in the PDK (process design kit) without any further cost. In terms of availability, the invention can be incorporated directly to the model library.
1) Malaysia Economy: The outcome of this project is a monolithic on-chip variable inductor that is suitable for mass production in CMOS process and used in the circuits for IoT applications. Using this product, one design constraint for CMOS IoT transceivers, which is frequency tuning, shall be reduced significantly. This environment will also inculcate more local players to form IC design houses. Malaysia will have enough talent for IC design to support multinational semiconductor industries investing in Malaysia.
2) Industry: This device can be offered using the integrated simulation of Cadence PDK and EM tool (Sonnet). The calibrated Sonnet process file will be given to customer as part of the design. This will add value to the design kits made available by Silterra to its customers and will attract more designers to use the PDK and also create higher confidence amongst designers to fabricate locally. This results in more customers for the foundry. Hence, economic gains for the local semiconductor foundry.